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Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
FB2033
FEATURES
* 8-bit transceivers * Latched, registered or straight through in either A to B or B to A
path
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
* Drives heavily loaded backplanes with equivalent load
impedances down to 10.
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Each BTL driver has a dedicated Bus GND for a signal return * Controlled output ramp and multiple GND pins minimize ground
bounce
* High drive 100mA BTL Open Collector drivers on B-port * Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Glitch-free power up/power down operation * Low ICC current * Tight output skew * Supports live insertion
TYPICAL 3.0 3.0 4.3 4.1 6 100 24 45 22 mA UNIT ns ns pF mA
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL ICC PARAMETER Propagation delay AIn to Bn Propagation delay Bn to AOn Output capacitance (B0 - Bn only) Output current (B0 - Bn only) AIn to Bn (outputs Low or High) Supply current Bn to AOn (outputs Low) Bn to AOn (outputs High)
ORDERING INFORMATION
PACKAGES 52-pin Plastic Quad Flat Pack (QFP) NOTE: Thermal mounting or forced air is recommended COMMERCIAL RANGE VCC = 5V10%; Tamb = 0C to +70C FB2033BB DRAWING NUMBER SOT379-1
PIN CONFIGURATION
LOGIC GND BG GND BG VCC LCAB BIAS V
SBA1
SBA0
AO0
AI1
AI0
OEA
VCC
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND AO1 AI2 AO2 AI3 AO3 LOOPBACK AI4 AO4 AI5 AO5 AI6 LOGIC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 LGOIC GND BUS GND AO6 AI7 AO7 LCBA OEB0 VCC SAB0 SAB1 VCC OEB1 B7 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
8-Bit Universal Transceiver FB2033 52-lead PQFP
B0 35 34 33 32 31 30 29 28 27
SG00068
1995 May 25
1
853-1717 15279
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
DESCRIPTION
The FB2033 is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level side. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A, SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a register, or a D-type latch. When configured in the buffer mode, the inverse of the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-High latch enables. Regardless of the mode, data is inverted from input to output. Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the Loopback input. When the Loopback input is High the output of the selected A-to-B logic element (not inverted) becomes the B-to-A input. The 3-State AO port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-State (AO port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (see the IEEE 1194.1 BTL standard). BTL features low power consumption
FB2033
by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The "VOH" clamp reduces inductive ringing effects during a Low-to-High transition. The "VOH" clamp is always active. The other clamp, the "trapped reflection" clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. To support live insertion, OEB0 is held Low during power on/off cycles to ensure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot. As with any high power device thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.
PIN DESCRIPTION
SYMBOL AI0 - AI7 AO0 - AO7 B0 - B7 OEB0 OEB1 OEA BUS GND LOGIC GND VCC BIAS V BG VCC BG GND SABn SBAn LCAB LCBA Loopback PIN NUMBER 50, 52, 3, 5, 8, 10, 12, 15 51, 2, 4, 6, 9, 11, 14, 16 40, 38, 36, 34, 32, 30, 28, 26 23 24 43 39, 37, 35, 33, 31, 29, 27, 25 1, 13, 17, 49 18, 22, 48 41 44 42 20, 21 45, 46 47 19 7 TYPE Input Output I/O Input Input Input GND GND Power Power Power GND Input Input Input Input Input Data inputs (TTL) 3-State outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the AO outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Live insertion pre-bias pin Band Gap threshold voltage reference Band Gap threshold voltage reference ground Mode select from AI to B Mode select from B to AO A-to-B clock/latch enable (transparent latch when High) B-to-A clock/latch enable (transparent latch when High) Enables loopback function when High (from AIn to AOn) NAME AND FUNCTION
1995 May 25
2
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
FUNCTION TABLE
INPUTS MODE AIn L H AIn to Bn transparent latch L H AIn to Bn latch and read l h AIn to Bn register Bn outputs latched and read (preconditioned latch) Bn to AOn thru mode L H X X X Bn to AOn transparent latch X X Bn to AOn latch and read X X Bn to AOn register AOn outputs latched and read (preconditioned latch) Disable Bn outputs Disable AOn outputs X X X X X X Bn* -- -- -- -- -- -- -- -- -- L H L H l h L H X X X X OEB0 H H H H H H H H H L L L L L L L L L L X X OEB1 L L L L L L L L L H H H H H H H H H X H X OEA L L L L L L L L L H H H H H H H H H X X L LCAB X X H H L X X X X X X X X X X X X LCBA X X X X X X X X X X X H H L X X X SAB1
0
FB2033
OUTPUTS SBA1
0
AOn Z Z Z Z Z Z Z Z Z H L H L H L H L latched data X X Z
Bn H** L H** L H** L H** L latched data input input input input input input input input X H** H** X
AIn to Bn thru mode
LL LL HX HX HX HX LH LH HX XX XX XX XX XX XX XX XX XX XX XX XX
XX XX XX XX XX XX XX XX XX LL LL HX HX HX HX LH LH HX XX XX XX
FUNCTION SELECT TABLE
MODE SELECTED Thru mode Register mode Latch mode SXX1 L L H SXX0 L H X
NOTES: H= L = h = l = X = Z = --= = = H** = Bn* =
High voltage level Low voltage level High voltage level one set-up time prior to the High-to-Low LCXX transition Low voltage level one set-up time prior to the High-to-Low LCXX transition Don't care High-impedance (OFF) state Input not externally driven Low-to-High transition High-to-Low transition Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
NOTE: In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn inputs are blocked out.
1995 May 25
3
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
LOGIC DIAGRAM
OEB0 OEB1 SAB0 SAB1 LCAB 23 24 20 21 47
FB2033
AIn
50
52, 2, 5, 8, 10, 12, 15
D En
40
Bn
D Clk 1 of 8 cells
38, 36, 34, 32, 30, 28, 26
LCBA SBA0 SBA1 OEA
19 45 46 43
D En AOn 51 D Clk 1 of 8 cells BGref Loopback 7 2, 4, 6, 9, 11, 14, 16
BGGnd
42
SG00069
1995 May 25
4
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
ABSOLUTE MAXIMUM RATINGS
FB2033
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Storage temperature AO0 - AOn B0 - Bn All inputs except B0 - Bn B0 - Bn PARAMETER RATING -0.5 to +7.0 -1.2 to +7.0 -1.2 to +3.5 -40 to +5.0 -0.5 to +VCC 48 200 -65 to +150 UNIT V V mA V mA C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH Supply voltage High-level input voltage Except B0 - Bn B0 - Bn Low-level input voltage Except B0 - Bn B0 - Bn Input clamp current High-level output current Low-level output current Off device input current Output capacitance of B port Operating free-air temperature range 0 Except B0 - Bn B0 - Bn AO0 - AOn AO0 - AOn B0 - Bn Except B0 - Bn, VI = 0 to 5.5V, VCC = 0V 6 PARAMETER LIMITS MIN 4.5 2.0 1.62 1.55 0.8 1.47 -40 -50 -3 24 100 100 7 +70 A pF C mA mA mA V NOM 5.0 MAX 5.5 UNIT V V
VIL
IIK IOH IOL IIA COB Tamb
1995 May 25
5
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IOFF VOH VOL PARAMETER High level output current Power-off output current High-level output voltage B0 - Bn B0 - Bn AO0 - AOn
4
FB2033
TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA Except B0-Bn VCC = MIN, II = IIK VCC = MIN, II = IIK 6 VCC = MIN, II = -18mA
LIMITS MIN TYP2 MAX 100 100 2.5 2.85 0.5 .75 0.5 -0.5 0.3 -1.2 50 20 100 100 -20 -100 50 -50 -45 24 45 22 -150 50 75 44 1.0 1.15
UNIT A A V
AO0 - AOn 4 Low-level output voltage B0 - Bn
V
VIK
Input clamp voltage B0 - Bn
V
II
Input current at maximum input voltage
Except B0-Bn Except B0-Bn
VCC = MAX, VI = 0.0V or 5.5V VCC = MAX, VI = 2.7V, Bn = AIn = 0V VCC = MAX, VI = 1.9V VCC = MAX, VI = 3.5V 5 VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.75V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX, VO = 0.0V VCC = MAX, outputs Low or High VCC = MAX, outputs Low VCC = MAX, outputs High
A A mA A A A mA
IIH
High-level input current B0 - Bn Except B0-Bn B0 - Bn
IIL IOZH IOZL IOS
Low-level input current Off-state output current Off-state output current Short-circuit output current 3
AO0 - AOn AO0 - AOn AO0 - AOn only AIn to Bn
ICC
Supply current (total)
Bn to AOn Bn to AOn
mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100A, but the parts will continue to function normally. 6. B0 - B7 clamps remain active for a minimum of 80ns following a High-to-Low transition.
1995 May 25
6
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
LIVE INSERTION SPECIFICATIONS
SYMBOL VBIASV Bias pin voltage PARAMETER VCC = 0 to 5.25V, Bn = 0 to 2.0V VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V Bus voltage during pre-bias Fall current during pre-bias Rise current during pre-bias Peak bus current during insertion Power up current Input glitch rejection B0 - B8 = 0V, Bias V = 5.0V B0 - B8 = 2V, Bias V = 4.5 to 5.5V B0 - B8 = 1V, Bias V = 4.5 to 5.5V VCC = 0 to 5.25V, B0 - B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns VCC = 0 to 5.25V, OEB0 = 0.8V VCC = 0 to 2.2V, OEB0 = 0 to 5V VCC = 5.0V 1.0 1.35 1.62 1 -1 10 LIMITS MIN 4.5 NOM
FB2033
MAX 5.5 1 10 2.1
UNIT V mA A V A A mA A ns
IBIASV
Bias pin DC current
VBn ILM IHM IBnPEAK IOLOFF tGR
100 100
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tTLH tTHL tSK(o) tSK(p) Maximum clock frequency Propagation delay (thru mode) Bn to AOn Propagation delay (transparent latch) Bn to AOn Propagation delay LCBA to AOn Propagation delay SBAn to AOn Propagation delay (Loopback mode) AIn to AOn Propagation delay (Loopback mode) Loopback to AOn Output enable time from High or Low OEA to AOn Output disable time to High or Low OEA to AOn Output transition time, AOn Port 10% to 90%, 90% to 10% Output to output skew, A port 1 Pulse skew 2 tPHL - tPLH MAX Waveform 4 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 5, 6 Waveform 5, 6 Test Circuit and Waveforms Waveform 3 Waveform 2 0.5 0.3 1.0 1.0 100 2.2 2.0 1.5 2.4 2.0 2.2 1.4 1.4 2.0 2.0 1.2 1.2 1.0 2.6 1.0 1.0 TYP 150 4.3 4.1 4.5 4.4 3.8 4.3 2.9 3.1 3.8 3.9 3.4 3.2 3.1 4.0 3.5 3.3 6.0 6.0 6.5 6.5 5.5 6.0 5.0 5.5 6.0 6.0 5.0 5.5 5.1 5.5 5.0 4.6 MAX Tamb = 0 to 70C, VCC = 5V10%, CL = 50pF, RL = 500 MIN 100 2.0 1.8 1.0 2.0 1.8 1.7 1.0 1.0 2.8 2.3 1.0 1.0 1.0 2.4 1.7 1.7 2.0 2.0 7.0 7.0 7.5 7.5 6.0 6.5 6.0 6.5 7.0 7.0 6.0 6.5 5.5 5.8 5.6 5.2 5.0 5.0 1.5 1.5 MAX MHz ns ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts. 2. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 3. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 May 25
7
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
AC ELECTRICAL CHARACTERISTICS (Continued)
B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CD = 30pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL V/t tSK(o) tSK(p) SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL V/t tSK(o) tSK(p) Propagation delay (thru mode) AIn to Bn Propagation delay (transparent latch) AIn to Bn Propagation delay LCAB to Bn Propagation delay SABn to Bn Enable/disable time OEB0 or OEB1 to Bn Output transition rate, Bn Port 20% to 80%, 80% to 20% Output to output skew, B port 1 Pulse skew 2 tPHL - tPLH MAX PARAMETER Propagation delay (thru mode) AIn to Bn Propagation delay (transparent latch) AIn to Bn Propagation delay LCAB to Bn Propagation delay SABn to Bn Enable/disable time OEB0 or OEB1 to Bn Output transition rate, Bn Port 20% to 80%, 80% to 20% Output to output skew, B port 1 Pulse skew tPHL - tPLH MAX
2
FB2033
Tamb = 0 to 70C, VCC = 5V10%, CD = 30pF, RU = 9 MIN 1.0 1.0 1.0 1.0 2.4 2.0 1.4 1.0 1.0 1.0 0.4 MAX 4.8 4.6 5.1 5.1 6.4 7.1 5.7 5.2 5.0 5.6 1.2 2.0
UNIT
TYP 2.9 2.9 3.1 3.3 4.4 5.1 3.6 3.3 3.0 3.1
MAX 4.3 4.4 4.5 4.8 5.7 6.6 5.0 4.9 4.5 5.0
Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test Circuit and Waveforms Waveform 3 Waveform 2 TEST CONDITION Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test Circuit and Waveforms Waveform 3 Waveform 2
1.2 1.0 1.4 1.0 2.7 2.2 1.8 1.0 1.4 1.0
ns ns ns ns ns V/ns ns ns
0.8 0.3 RU = 16.5 1.2 1.0 1.4 1.0 2.7 2.2 1.8 1.0 1.4 1.0 3.0 3.0 3.2 3.4 4.5 5.2 3.7 3.4 3.1 3.2
1.5 1.5
RU = 16.5 4.4 4.5 4.6 4.9 5.8 6.7 5.1 5.0 4.6 5.1 1.0 1.0 1.0 1.0 2.4 2.0 1.4 1.0 1.0 1.0 0.2 4.9 4.7 5.2 5.2 6.5 7.2 5.8 5.3 5.1 5.7 0.6 1.5 1.5
UNIT ns ns ns ns ns V/ns ns ns
0.5 0.3
1.0 1.0
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 May 25
8
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
AC SETUP REQUIREMENTS
LIMITS TEST CONDITION Tamb = +25C, VCC = 5V
FB2033
SYMBOL
PARAMETER
Tamb = 0 to 70C, VCC = 5V10%
UNIT
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 9 (B side) MIN TYP MAX MIN 4.0 4.0 1.3 1.3 4.0 4.0 MAX ns ns ns UNIT ns ns ns 3.0 3.0 1.0 1.0 3.0 3.0
ts(H) ts(L) th(H) th(L) tw(H) tw(L) SYMBOL ts(H) ts(L) th(H) th(L) tw(H) tw(L)
Setup time AIn to LCAB or Bn to LCBA Hold time AIn to LCAB or Bn to LCBA Pulse width, High or Low LCAB or LCBA PARAMETER Setup time AIn to LCAB or Bn to LCBA Hold time AIn to LCAB or Bn to LCBA Pulse width, High or Low LCAB or LCBA
Waveform 4 Waveform 4 Waveform 4 TEST CONDITION Waveform 4 Waveform 4 Waveform 4
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 16.5 (B side) 3.0 3.0 1.0 1.0 3.0 3.0 4.0 4.0 1.3 1.3 4.0 4.0
AC WAVEFORMS
Input VM tPLH Output VM VM tPHL VM Output Input VM tPHL VM VM tPLH VM
AIn, Bn
VM tSK(o)
AIn, Bn
AOn, Bn
VM
LCAB, LCBA
Waveform 3. Output to Output Skew
Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency
OEA
VM tPZH
VM tPHZ VM VOH -0.3V OV AOn OEA VM tPZL VM VM tPLZ VOL +0.3V
AOn
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
1995 May 25
9
IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII
VM
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 2. Propagation Delay for Data or Output Enable to Output
ts
th
VM
ts tw(L)
th
tw(H)
VM
1/fMAX
SG00070
Philips Semiconductors
Product specification
8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V RL NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10%
FB2033
90%
AMP (V)
VIN PULSE GENERATOR RT D.U.T.
VOUT
LOW V tTLH
(tf) (tr)
90% VM tW
(tr) (tf)
AMP (V)
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open
VCC BIAS V VIN PULSE GENERATOR RT D.U.T. 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions Family FB+ A Port B Port INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.0ns
500ns 2.5ns 500ns 2.0ns
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00063
1995 May 25
10

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